Projects
Software
Coming soon...
Electronics
My father was an electrical engineer at Bell Labs for his entire professional life and was involved directly in the creation of technologies related to ISDN and DSL. Although I didn't choose to follow in his footsteps in my career, I am still fascinated by electronics and I continue to be an avid hobbyist and tinkerer.
These are some of the projects that I work on in my spare time.
JOP
JOP is the creation of Martin Schoeberl and is an open-source Java processor implemented in VHDL for use in commonly available FPGA devices. I've assisted Martin in porting it to work with Xilinx FPGA's.
For more information, visit JopDesign.
BlockGen
Created to assist in the porting of JOP, but generally very useful when creating designs for Xilinx devices. BlockGen is a Java command-line application that generates a memory module in VHDL using Xilinx Synchronous Block RAM with the given parameters. Input file should be in Xilinx COE (.coe) format, Altera MIF (.mif) format, or be a text file with hex data that can be extracted. If no input file is specified, an uninitialized memory module will be generated.
Download it here (Last updated Feb 10, 2004 8:01am PST).
61k zip file, source code included.
MakeEagleSymbol
Command line tool for Windows created to assist in the creation of library parts for use in the EAGLE Layout Editor ECAD design tool.
Download it here (Last updated June 1, 2004 10:05am PST).
20k zip file, source code included.
OpenBMW
OpenBMW is a web site and mailing list I started for automotive hackers who want to understand how the in-car electronics of BMW automobiles work.
For more information, visit OpenBMW.
Coming soon...
Electronics
My father was an electrical engineer at Bell Labs for his entire professional life and was involved directly in the creation of technologies related to ISDN and DSL. Although I didn't choose to follow in his footsteps in my career, I am still fascinated by electronics and I continue to be an avid hobbyist and tinkerer.
These are some of the projects that I work on in my spare time.
JOP
JOP is the creation of Martin Schoeberl and is an open-source Java processor implemented in VHDL for use in commonly available FPGA devices. I've assisted Martin in porting it to work with Xilinx FPGA's.
For more information, visit JopDesign.
BlockGen
Created to assist in the porting of JOP, but generally very useful when creating designs for Xilinx devices. BlockGen is a Java command-line application that generates a memory module in VHDL using Xilinx Synchronous Block RAM with the given parameters. Input file should be in Xilinx COE (.coe) format, Altera MIF (.mif) format, or be a text file with hex data that can be extracted. If no input file is specified, an uninitialized memory module will be generated.
Download it here (Last updated Feb 10, 2004 8:01am PST).
61k zip file, source code included.
MakeEagleSymbol
Command line tool for Windows created to assist in the creation of library parts for use in the EAGLE Layout Editor ECAD design tool.
Download it here (Last updated June 1, 2004 10:05am PST).
20k zip file, source code included.
OpenBMW
OpenBMW is a web site and mailing list I started for automotive hackers who want to understand how the in-car electronics of BMW automobiles work.
For more information, visit OpenBMW.
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